1. Field of the Invention
The present invention relates generally to code tracking systems and methods for use in a code division multiple access (CDMA) communication system, and particularly, in a direct sequence code division multiple access (DS-CDMA) communication system, or in a phase lock loop.
2. Description of the Related Art
In direct sequence code division multiple access systems, the performance of a code tracking loop affects the system performance greatly. In turn, the performance of the code tracking loop is dependent on the receiving environment of the receiver. The mean-time-to-lose-lock (MTLL) is an important performance criterion of the tracking loop. Ideally, events of losing lock should be as rare as possible; in other words, MTLL should be maximized.
Major factors introducing high occurrences of lockloss events include fading and high chip rate. In a multi-path fading or high chip rate environment, the change rate of the received signal is very fast. This phenomenon occurs particularly when the speed of the mobile unit is fast or the signal-to-noise ratio is low.
The receiver of a spread spectrum communication system should be able to adapt to a fast change in different environments without ceasing operation. In mobile radio communications, mobile units move quickly under various fading environments To receive a signal effectively, it is necessary to track the changes of the reception signal. Therefore, the receiver of the spread spectrum communication system generally has a synchronous tracking function for adapting to any change in the receiving environment.
In general, code tracking loops for spread spectrum communication systems can be classified as coherent and non-coherent tracking loops. The difference between coherent and non-coherent loops is that coherent loops use received carrier phase information as a reference, whereas non-coherent loops do not. Many coherent loops use correlation processing among the received signals, the early and late phase of received waveforms; such circuits are commonly referred to as delay-lock loops (DLL).
U.S. Pat. No. 5,299,229 discloses a spread spectrum receiver having a code tracking system for use with respect to a high rate pseudo-noise (PN) composite code formed of two PN codes, a high rate PN code and a low rate PN code. This patent provides a method for tracking the high rate PN code or the low rate PN code according to a data ratio in the tracking loop for a variable system.
U.S. Pat. No. 5,737,362 discloses a double delay-lock loop code tracking system for enlarging a linear section of an energy detecting area of the tracking loop by generating a code having numerous time differences relative to the midpoint of a chip as a timing reference. This patent uses an error detection unit for deciding the final output to the loop filter from a received energy of a signal de-spread by an early code advanced as much as Δ and 2Δ and an energy of a signal de-spread by a late code delayed as much as Δ and 2Δ. The error energy detecting unit computes the results from these values, then outputs a control signal to a voltage controlled oscillator (VCO). The algorithm used for the error energy detecting unit enlarges the linear section of the tracking loop. Therefore, the system is more adaptive to track a signal under a fast changing environment. The disclosure of the above patents are incorporated by reference herein in their entireties.
A conventional delay-lock loop code tracking system comprises a phase discriminator, a loop filter and VCO, and a spread waveform generator (PN code generator). After demodulation, the received signal is input to the delay-lock discriminator where it is correlated with an early spreading pseudo-noise (PN) code advanced as much as Δ/2, and a late spreading PN code delayed as much as Δ/2. The parameter A is the total normalized time difference between the early and late discriminator channel (i.e., usually a chip).
FIG. 1 shows a general delay-lock code tracking loop comprising correlate-and-dump (or integrate-and-dump) units 10A, 10B, a local PN code generator 20, a VCO 30, a loop filter 40, and a tracking code decision unit 50. The code tracking loop receives an input signal on line 1, which consists of real and imaginary components. These components are provided to the correlate-and-dump units 10A, 10B where they are correlated by an early or late code generated by the local PN code generator 20. The energy obtained from correlate-and-dump units 10A, 10B for the early and late codes are supplied to the code tracking decision unit 50. The results computed by the code tracking decision unit 50 are used to adjust the correct time reference control for the local PN code generator 20. The adjustment is done by a loop filter 30 and voltage controlled oscillator 40. The PN code tracking of the DLL decision unit 50 is carried out conventionally by subtracting and processing the energy of two shifted versions of the auto-correlation finction of the early and late PN codes in order to obtain a nonlinear discriminator characteristic (S curve). The S curve possesses a zero-crossing at the on-time code position, which is needed for de-spreading and data modulation. The most important issue in designing a PN code tracking device is to be able to track as closely as possible the midpoint of a chip in a case where Doppler effects and channel noise disturb the loop operation.
Due to the finite width of the S curve, a sharp and short disturbance can push the tracking loop out of the locked region (i.e., lockloss). Thereafter, the receiver cannot resynchronize itself without restarting code acquisition. Code acquisition is a more time consuming process than code tracking. Thus, lockloss is undesirable and should be minimized.